Design Linked Incentive

About the Scheme

The Design Linked Incentive Scheme aims to offer financial incentives as well as design infrastructure support across various stages of development and deployment of semiconductor design(s) for Integrated Circuits (ICs), Chipsets, System on Chips (SoCs), Systems & IP Cores and semiconductor linked design(s) over a period of 5 years.

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Design Linked Incentive Scheme 21 December, 2021

Guidelines for Design Linked Incentive Scheme 30 December, 2021

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Design Linked incentive Scheme

Semiconductors are at the heart of all electronic products and constitute a significant share in the Bill of Material (BOM). The National Policy on Electronics 2019 aims to position India as a global hub for Electronics System Design and Manufacturing (ESDM) and envisions creation of a vibrant semiconductor chip design ecosystem in the country. With an exceptional talent pool of 20% of world's semiconductor design engineers and thousands of chips designed by them every year in the country, India is poised for growth to achieve self-reliance and technology leadership in semiconductor design sector.
Ministry of Electronics and Information technology has announced the Design Linked Incentive Scheme to offset the disabilities in the domestic industry involved in semiconductor design in order to not only move up in value-chain but also strengthen the semiconductor chip design ecosystem in the country. CDAC is responsible for implementation of the DLI Scheme as Nodal Agency.

Objective

To attract large investments for setting up semiconductor wafer fabrication facilities in the country to strengthen the electronics manufacturing ecosystem and help establish a trusted value chain.

Eligibility

Companies / Consortia / Joint Ventures proposing to set up a Silicon CMOS based Semiconductor Fab in India for manufacturing Logic / Memory / Digital ICs / Analog ICs / Mixed Signal ICs / SoCs

Tenure of the Scheme

Support under the scheme shall be provided for a period of six years. The tenure of the actual fiscal support outflow may be extended based on the approval of the Minister of Electronics and Information Technology.

Procedure to Apply